1/4 rev. b structure silicon monolithic integrated circuit product i2c bus 128kbit (16, 3848bit) eeprom part number BU9897GUL-W part number package BU9897GUL-W vcsp50l2 features two wire serial interface wide operating voltage range (1.7v5.5v) endura nce : 1,000,000 erase/write cycles absolute maximum rating (ta=25) parameter symbol rating unit supply voltage vcc -0.36.5 v power dissipation pd 220 *1 mw storage temperature tstg -65125 operating temperature topr -4085 terminal voltage -0.3vcc+1.0 *2 v *1 2.2mw/(*1) for operation above 25 *2 the max value of terminal voltage is not over 6.5v recommended operating condition parameter symbol rating unit supply voltage vcc 1.75.5 v input voltage vin 0vcc v
2/4 rev. b memory cell characteristics (ta=25, vcc=1.75.5v) parameter specification unit min. typ. max. write/erase cycle *1 1,000,000 - - cycles data retention *1 40 - - years initial data ffh in all address. *1 not 100% tested dc operating characteristics parameter symbol specification unit specification min. min. min. "h" input voltage1 vih1 0.7vcc vcc+1.0 v "l" input voltage1 vih2 -0.3 0.3vcc v "l" output voltage1 vol1 0.4 v iol=3.0ma 2.5v Q vcc Q 5.5v sda "l" output voltage2 vol2 0.2 v iol=0.7ma 1.7v Q vcc 2.5v sda input leakage current ili -1 1 a vin=0v vcc output leakage current ilo -1 1 a vout=0vvcc sda operating current icc1 2.5 ma vcc=5.5v,fscl=400 hz twr=5ms b y te write,pa g e write icc2 0.5 a vcc=5.5v,fscl=400 hz random read,current read,sequential read standby current isb 2.0 a vcc=5.5v,sda,scl=vcc a0,a1,a2=gnd,wp=gnd ac operating characteristics (unless otherwise specified ta=-4085, vcc=1.75.5v) parameter symbol specification unit min. typ. max. clock frequency fscl 400 khz data clock high period thigh 0.6 s data clock low period tlow 1.2 s sda and scl rise time *1 tr 0.3 s sda and scl fall time *1 tf 0.3 s start condition hold time thd:sta 0.6 s start condition setup time tsu:sta 0.6 s input data hold time thd:dat 0 ns input data setup time tsu:dat 100 ns output data dela y time tpd 0.1 0.9 s output data hold time tdh 0.1 s stop condition setup time tsu:sto 0.6 s bus free time tbuf 1.2 s write cycle time twr 5 ns noise spike width (sda and scl ) ti 0.1 s wp hold time thd:wp 0 ns wp setup time tsu:wp 0.1 s wp high period thigh:wp 1.0 s pin no. pin name a1 scl a2 wp a3 vcc a4 gnd b1 sda b3 a0 b4 gnd c1 gnd c2 a2 c3 a1 c4 gnd a3 a2 a1 b1 c1 c2 c3 b3 sda scl wp vcc gnd a2 a1 a0 128kbit eeprom array address decoder slave, word address register data register control logic high voltage gen. v cc level detect 14bit 14bit 8bit ack start stop pin no. name fig.-1 block diagram block diagram *1 not 100% tested
3/4 rev. b notes for power supply vcc rises through the low voltage region in which internal circ uit of ic and the controller are unstable, so that device may n ot work properly due to an incomplete reset of internal circuit. to prevent this, the device has the feature of p.o.r. and lvcc. in th e case of power up, keep the following conditions to ensure functions of p.o.r. and lvcc. 1. it is necessary to be "sda='h '" and "scl='l' or 'h'". 2. follow the recommended conditions of tr, toff, vbot for the fun ction of p.o.r. during power up. 3. prevent sda and scl from being "high-z". in case that condition 1. and/or 2. cannot be met, take following actions. a unable to keep condition 1. ( sda is "low" during power up.) control sda ,scl to be "high" as fig.-3(a), 3(b). bunable to keep condition 2. after power becomes stable, execute cunable to keep both conditions 1 and 2. follow the instruction a fi rst, then the instruction b. cautions on use (1) absolute maximum ratings if the absolute maximum ratings such as impressed voltage and a ction temperature range and so forth are exceeded, lsi may be destructed. do not impress vol tage and temperature exceeding the absolute maximum ratings. in the case of fear exceeding the absolute maximum ratings, ta ke physical safety countermeasu res such as fuses, and see to it that conditions exceeding the absolute maximum ratings sho uld not be impre ssed to lsi. (2) gnd electric potential set the voltage of gnd terminal lowest at any action condition. make sure that each terminal voltage is not lower than that of gnd terminal. (3) thermal design in consideration of permissible loss in actual use condition, c arry out heat design with sufficient margin. (4) terminal to terminal shortcircuit and wrong packaging when to package lsi onto a board , pay sufficient attention to l si direction and disp lacement. wrong packaging may destruct lsi. and in the case of shortcircuit between lsi terminals and terminals and power source, terminal and gnd owing to foreign matter, lsi may be destructed. (5) use in a strong e lectromagnetic field may cause malfunction , therefore, evaluated design sufficiently. tr toff vbot 0 fig.-2 vcc rising waveform vcc recommended conditions of tr, toff, vbot tlow tsu:dat tdh after vcc becomes stable scl vcc sda fig.-3a scl='h' and sda='l' tsu:dat after vcc becomes stable fig.-3b scl='l' and sda='l'
4/4 rev. b fig.-1 physical dimension (unit:mm) scl vcc gnd sda wp a2 a1 a0 gnd gnd gnd the a4, b4, c4 pins are set to gnd inside chip. please set these open. please dont connect these gnd. 9897 lot no.
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